2.73. 2D Convolution Batch Normalization Scaling
Calculates the output by performing a 2D convolution on input data, applying batch normalization to standardize the features, and scaling the result by a constant factor.
Progress
Optimization Timeline
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Reasoning
In this model the original operations are a convolution, batch normalization (BN) and an element‐wise scaling. During inference the BN layer uses its running statistics to normalize the convolution output and then applies an affine transformation. After that, the whole result is scaled. To reduce memory bandwidth and kernel launch overhead we can fuse BN and scaling into a single custom CUDA kernel. In this kernel each element y at index corresponding to channel c is computed as: y = [ (x – mean[c]) / sqrt(var[c] + eps) * weight[c] + bias[c] ] * scaling_factor. We assume that BN is in evaluation mode so that running_mean, running_var, weight, bias and eps are fixed constants. The fused kernel computes the element‐wise transformation where the channel index is computed from the flattened index. We use c10::cuda::CUDAGuard to guarantee operations execute on the proper device. In our Python module we keep the convolution (which is best handled by cuDNN) while fusing BN and scaling using our custom CUDA kernel. In the forward pass of our CUDAModel, if BN is in training mode we fall back to the standard BN and scaling; otherwise we extract the BN parameters (running_mean, running_var, weight, bias, and eps) and call our fused CUDA extension. This approach avoids multiple kernel launches and intermediate memory writes, and has the potential to speed up inference by fusing multiple pointwise operations. Before finishing, we ask: Have my improvements genuinely helped? Yes—the fused elementwise transformation reduces memory traffic and kernel launch overhead, providing a true speedup.
#include <torch/extension.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda_runtime.h>
#include <math.h>
// Fused BatchNorm and scaling kernel.
// For an input tensor of shape [N, C, H, W], each thread computes one element.
// The BN parameters are broadcast along H and W.
__global__ void bn_scale_kernel(const float* __restrict__ input,
float* __restrict__ output,
const float* __restrict__ mean,
const float* __restrict__ var,
const float* __restrict__ weight,
const float* __restrict__ bias,
int N, int C, int H, int W,
float eps,
float scaling_factor) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int total = N * C * H * W;
if (index < total) {
int hw = H * W;
// Determine channel index.
int c = (index / hw) % C;
float x = input[index];
float norm = (x - mean[c]) / sqrtf(var[c] + eps);
float bn_out = norm * weight[c] + bias[c];
output[index] = bn_out * scaling_factor;
}
}
// Fused forward function: applies batch normalization (in eval mode) and scaling.
torch::Tensor bn_scale_forward(torch::Tensor input,
torch::Tensor running_mean,
torch::Tensor running_var,
torch::Tensor bn_weight,
torch::Tensor bn_bias,
float eps,
float scaling_factor) {
// Ensure we are operating on the correct CUDA device.
c10::cuda::CUDAGuard device_guard(input.device());
// Input is expected to be of shape [N, C, H, W].
TORCH_CHECK(input.dim() == 4, "Input must be a 4D tensor");
int N = input.size(0);
int C = input.size(1);
int H = input.size(2);
int W = input.size(3);
auto output = torch::empty_like(input);
int total = N * C * H * W;
int threads = 256;
int blocks = (total + threads - 1) / threads;
bn_scale_kernel<<<blocks, threads, 0, c10::cuda::getCurrentCUDAStream()>>>(
input.data_ptr<float>(),
output.data_ptr<float>(),
running_mean.data_ptr<float>(),
running_var.data_ptr<float>(),
bn_weight.data_ptr<float>(),
bn_bias.data_ptr<float>(),
N, C, H, W,
eps,
scaling_factor
);
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("bn_scale_forward", &bn_scale_forward, "Fused BatchNorm (eval mode) and scaling (CUDA)");
}