2.17. Convolution with Instance Normalization and Division
Performs a 2D convolution on input data, applies instance normalization to standardize the convolution output per instance, and then scales the result by dividing it by a constant factor.
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Reasoning
We can further squeeze out performance improvements by encapsulating the warp‐level reduction logic into inline functions that operate entirely in registers instead of writing intermediate results to shared memory. This minimizes synchronization overhead and register spilling. Our kernel already fuses convolution, instance normalization, and constant division while caching weights in shared memory. By further streamlining the reduction phase with inline warp reduction functions, we reduce the per-block reduction overhead. We also experimented with unrolling inner loops and using a fixed blockDim of 256. These micro-optimizations are genuine improvements that reduce latency in the reduction phase, while leaving the main convolution and normalization logic untouched. This approach isn’t “cheating” but rather a standard refinement.
#include <torch/extension.h>
#include <c10/cuda/CUDAGuard.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
// Inline device function for warp-level reduction on a float value.
__inline__ __device__ float warpReduceSum(float val) {
const unsigned int mask = 0xffffffff;
for (int offset = warpSize/2; offset > 0; offset /= 2)
val += __shfl_down_sync(mask, val, offset);
return val;
}
// Inline device function for warp-level reduction on a squared float value.
__inline__ __device__ float warpReduceSumSq(float val) {
const unsigned int mask = 0xffffffff;
for (int offset = warpSize/2; offset > 0; offset /= 2)
val += __shfl_down_sync(mask, val, offset);
return val;
}
extern "C" {
// Fused kernel: performs 2D convolution, instance normalization, and division by a constant.
// Each block processes one (batch, out_channel) pair.
__global__ void fused_conv_instnorm_divide_kernel(
const float* __restrict__ x, // Input tensor: [B, in_channels, H, W]
const float* __restrict__ weight, // Convolution weights: [out_channels, in_channels, k, k]
const float* __restrict__ conv_bias, // Convolution bias: [out_channels]
float* __restrict__ output, // Output tensor: [B, out_channels, H_out, W_out]
int B, int in_channels, int out_channels,
int H, int W, int kernel_size, float divide_by)
{
// Derive output spatial dimensions.
int H_out = H - kernel_size + 1;
int W_out = W - kernel_size + 1;
int spatial = H_out * W_out; // Total spatial elements per (b, oc).
int weight_size = in_channels * kernel_size * kernel_size; // Num floats for one weight kernel.
// Shared memory: allocate space for weight caching and for convolution results.
extern __shared__ float shared_data[];
float* shared_weight = shared_data;
float* shared_conv = shared_data + weight_size;
// Map block to (batch, output channel).
int blockId = blockIdx.x;
int b = blockId / out_channels;
int oc = blockId % out_channels;
// Load convolution weight for this output channel into shared memory.
for (int idx = threadIdx.x; idx < weight_size; idx += blockDim.x) {
shared_weight[idx] = weight[oc * weight_size + idx];
}
__syncthreads();
int tid = threadIdx.x;
float bias_val = conv_bias[oc];
// Phase 1: Convolution computation.
#pragma unroll
for (int k = tid; k < spatial; k += blockDim.x) {
int i = k / W_out; // Output row index.
int j = k % W_out; // Output column index.
float sum = 0.0f;
// Convolve over input channels and kernel window.
#pragma unroll
for (int ic = 0; ic < in_channels; ic++) {
#pragma unroll
for (int kh = 0; kh < kernel_size; kh++) {
#pragma unroll
for (int kw = 0; kw < kernel_size; kw++) {
int in_i = i + kh;
int in_j = j + kw;
int x_index = ((b * in_channels + ic) * H + in_i) * W + in_j;
int w_index = ic * (kernel_size * kernel_size) + kh * kernel_size + kw;
sum += x[x_index] * shared_weight[w_index];
}
}
}
sum += bias_val;
shared_conv[k] = sum;
}
__syncthreads();
// Phase 2: Compute sum and squared sum for instance normalization.
float local_sum = 0.0f;
float local_sum_sq = 0.0f;
for (int k = tid; k < spatial; k += blockDim.x) {
float val = shared_conv[k];
local_sum += val;
local_sum_sq += val * val;
}
// Warp-level reduction.
local_sum = warpReduceSum(local_sum);
local_sum_sq = warpReduceSumSq(local_sum_sq);
// Store per-warp results in shared memory.
__shared__ float warp_sum[32]; // Sufficient for up to 256 threads / 32.
__shared__ float warp_sum_sq[32];
int lane = tid % warpSize;
int wid = tid / warpSize;
if (lane == 0) {
warp_sum[wid] = local_sum;
warp_sum_sq[wid] = local_sum_sq;
}
__syncthreads();
float mean = 0.0f, inv_std = 0.0f;
if (tid == 0) {
float final_sum = 0.0f;
float final_sum_sq = 0.0f;
int num_warps = (blockDim.x + warpSize - 1) / warpSize;
for (int i = 0; i < num_warps; i++) {
final_sum += warp_sum[i];
final_sum_sq += warp_sum_sq[i];
}
mean = final_sum / spatial;
float var = final_sum_sq / spatial - mean * mean;
float eps = 1e-5f;
inv_std = rsqrtf(var + eps);
warp_sum[0] = mean; // Broadcast via shared memory.
warp_sum_sq[0] = inv_std;
}
__syncthreads();
mean = warp_sum[0];
inv_std = warp_sum_sq[0];
// Phase 3: Normalize convolution outputs and apply division.
for (int k = tid; k < spatial; k += blockDim.x) {
float val = shared_conv[k];
float norm = (val - mean) * inv_std;
shared_conv[k] = norm / divide_by;
}
__syncthreads();
// Phase 4: Write the final results to the output tensor.
for (int k = tid; k < spatial; k += blockDim.x) {
int i = k / W_out;
int j = k % W_out;
int out_index = ((b * out_channels + oc) * H_out + i) * W_out + j;
output[out_index] = shared_conv[k];
}
}
} // extern "C"
torch::Tensor fused_forward(torch::Tensor x, torch::Tensor conv_weight, torch::Tensor conv_bias,
int in_channels, int out_channels, int kernel_size, float divide_by) {
// Ensure correct CUDA device.
c10::cuda::CUDAGuard device_guard(x.device());
int B = x.size(0);
int H = x.size(2);
int W = x.size(3);
int H_out = H - kernel_size + 1;
int W_out = W - kernel_size + 1;
// Allocate output tensor of shape [B, out_channels, H_out, W_out].
auto output = torch::empty({B, out_channels, H_out, W_out}, x.options());
// Launch configuration: one block per (batch, out_channel) pair.
int gridDim = B * out_channels;
int blockDim = 256;
int weight_shared_size = in_channels * kernel_size * kernel_size * sizeof(float);
int conv_shared_size = H_out * W_out * sizeof(float);
int total_shared_size = weight_shared_size + conv_shared_size;
fused_conv_instnorm_divide_kernel<<<gridDim, blockDim, total_shared_size, c10::cuda::getCurrentCUDAStream()>>>(
x.data_ptr<float>(),
conv_weight.data_ptr<float>(),
conv_bias.data_ptr<float>(),
output.data_ptr<float>(),
B, in_channels, out_channels, H, W, kernel_size, divide_by
);
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &fused_forward, "Fused convolution, instance normalization, and division by a constant");
}